1. Field of the Invention
The present invention relates to a time setting device and method of an operating system in a power saving mode, and, more particularly, to a time setting device and method for setting the time and date in a central processing unit restarted after having its clock stopped during a power saving mode of the operating system.
2. Description of the Prior Art
Recently design efforts have sought to provide energy saving features to the functional aspects of computers. Accordingly, power saving functions have been developed and applied to the operational systems of computers. Presently, most computer systems use a power management technique havng a power saving feature dedicated to reducing the consumption of electrical power during a standby mode when the computer system is not operating upon data. Generally, the motor of a hard disc drive is stopped in order to reduce the power consumed during the standby mode, and the chipsets in the computer system are set into a power saving mode such as a standby mode or a suspend mode. It is difficult, however, to satisfy power of less than 30 Watts, a standard established by the Environmental Protection Agency, without stopping the clock of the central processing unit such as a 486 DX or a P5 pentium microprocessor, and thereby placing the chipset for the central processing unit into a power saving mode with its clock stopped.
Accordingly, when the central processing unit returns to a normal state by an activity through an input operation by a keyboard or a mouse, all of the operations of the computer return to a previous state with the central processing unit being returned to an operating state. I have found that conventional power management schemes for a computer delay the operational time and date of the operating system by as much as the time interval during which the central processing unit was stopped because the commands for the central processing unit are not performed during the powering saving mode and consequently, the time keeping function of the operating system is stopped while the central processing unit is in the power saving mode. Recent power management schemes such as the Computer-Controlled Circuit Breaker Energy Management Arrangement Having Reliable Memory And Clock, U.S. Pat. No. 5,315,499 of Ron J. Bilas, et alii, have sought to use a charged capacitor to maintain continuous operation of a real time clock circuit during power outages. This scheme also depends however, upon operation of the central processor unit to periodically store images of the real time during normal operation.